1. Field of the Invention
The present invention generally relates to the field of data bus systems. More particularly, the present invention relates to the field of synchronizing local clocks in a data bus system.
2. Related Art
The 1394 Serial Bus Standard (or 1394 Standard) is a protocol for a high performance digital serial data bus. The 1394 Standard provides a versatile, high-speed method of interconnecting a variety of devices (e.g., computer system, digital camera, digital VCR, TV settop box, digital camcorder, storage device, digital audio device, etc.). Moreover, the 1394 Standard enables a wide range of applications, including desktop video editing, publishing, data storage, video conferencing, and home Audio/Video networking. Rapid embrace of the 1394 Standard has been spurred by the emergence of digital video and multimedia applications.
The 1394 Standard offers many advantages over other technologies. The major advantages include very high speed data transfer rates, self-configuring, plug-and-play operation, both asynchronous data transfer (guaranteed delivery) and isochronous data transfer (guaranteed bandwidth with low overhead), and flexible topology.
The 1394 Standard was originally adopted in 1995 as the 1394-1995 specification. Later, the original specification was revised, providing some clarification on the original specification, changing some optional portions of the original specification to mandatory, and adding some performance enhancements. The first revision was approved and is known as the 1394a specification. A second revision of the 1394 Standard is known as the 1394b specification. The 1394b specification represents a significant enhancement of the 1394 Standard.
FIG. 1 illustrates the well-known protocol layers of the 1394 Standard, whereas each device compliant with the 1394 Standard implements the protocol layers. The 1394 Standard includes a transaction layer 20, a link layer 30, a physical layer 40, and a serial bus management layer 60. The protocol layers interact and interface with the host 10 (e.g., processor, PCI Bus, application, etc.) and with the 1394 connector, whereas the 1394 connector physically couples one device to another device. Each protocol layer is implemented as circuitry, software, or both.
The physical layer 40 is responsible for the clocking scheme of the 1394 Standard. The physical layer 40 maintains a local clock, whereas each device has a respective local clock. Data transmissions from a transmitting device to a receiving device are synchronized by the local clock of the transmitting device. The transmitting device transmits data and its local clock to the receiving device. The receiving device recovers the local clock of the transmitting device and utilizes the recovered local clock to recover the data transmitted by the transmitting device.
FIG. 2 illustrates a conventional 1394b data bus system 200 according to the prior art, showing the conventional clocking scheme of the prior art. The conventional 1394b data bus system 200 includes a plurality of nodes 210A-210F. Each node is a device (e.g., computer system, digital camera, digital VCR, TV settop box, digital camcorder, storage device, digital audio device, etc.) which is compliant with the 1394b specification. One of the plurality of nodes is designated as a root node according to the 1394b specification. Here, node A 210A is the root node 210A.
Each node 210A-210F includes an oscillator 215A-215F for generating a respective local clock 220A-220F or CLK A-CLK F, whereas each local clock 220A-220F operates at a nominal frequency of 25 MHz. Moreover, each node 210A-210F includes a cycle counter 230A-230F for coordinating time dependent data (e.g., digital video data, digital audio data, etc.). Each cycle counter 230A-230F is incremented by a respective local clock 220A-220F. In addition, each node 210A-210F includes a buffer 240A-240F for storing data which is to be transmitted to another node or which has been received from another node.
Node A 210A includes a port 262A coupled to a phase locked loop 252A, a port 264A coupled to a phase locked loop 254A, and a port 266A coupled to a phase locked loop 256A. Node B 210B includes a port 262B coupled to a phase locked loop 252B and a port 264B coupled to a phase locked loop 254B. Node C 210C includes a port 262C coupled to a phase locked loop 252C. Node D 210D includes a port 262D coupled to a phase locked loop 252D. Node E 210E includes a port 262E coupled to a phase locked loop 252E and a port 264E coupled to a phase locked loop 254E. Node F 210F includes a port 262F coupled to a phase locked loop 252F.
According to the 1394b specification, each node 210A-210F assigns a parent port identifier (illustrated by xe2x80x9cPxe2x80x9d) to a port to indicate that a node which is closer to the root node 210A is coupled to that port. Moreover, each node 210A-210F assigns a child port identifier (illustrated by xe2x80x9cCxe2x80x9d) to a port to indicate that a node which is farther away from the root node 210A is coupled to that port. For example, the port 262B of node B 210B is a parent port because port 262B is coupled to node A 210A, which is a node that is actually the root node 210A. Similarly, the port 262C of node C 210C is a parent port because port 262C is coupled to node B 210B, which is a node that is closer to the root node 210A. Moreover, the port 262A of node A 210A (the root node) is a child port because port 262A is coupled to node B 210B, which is a node that is farther from the root node 210A. Similarly, the port 264B of node B 210B is a child port because port 264B is coupled to node C 210C, which is a node that is farther from the root node 210A.
Node A 210A transmits data via data connections 271, 276, and 278. Node B 210B transmits data via data connections 272 and 273. Node C 210C transmits data via data connection 274. Node D 210D transmits data via data connection 275. Node E 210E transmits data via data connections 277 and 270. Node F 210F transmits data via data connection 279. Each data connection 270-279 is a twisted wire pair.
According to the 1394b specification, a transmitting node (e.g., node A 210A) uses its local clock (e.g., CLK A) to synchronize transmission of data packets to the receiving node (e.g., node B 210B) via a data connection (e.g., data connection 271). The transmitting node (e.g., node A 210A) encodes on a single twisted wire pair (e.g., data connection 271) the data packets and its local clock (e.g., CLK A) using a 8B10B coding. The receiving node (e.g., node B 210B) utilizes a phase locked loop (e.g., phase locked loop 252B) (which is coupled to the port that is coupled to the transmitting node) to recover the local clock (e.g., CLK A) of the transmitting node (e.g., node A 210A). The receiving node (e.g., node B 210B) utilizes the recovered local clock (e.g., CLK A) to recover the data packets transmitted via a data connection (e.g., data connection 271). If the receiving node (e.g., node B 210B) retransmits the data packets to another node (e.g., node C 210C), the receiving/retransmitting node (e.g., node B 210B) uses its local clock (e.g., CLK B) to synchronize transmission of data packets to a second receiving node (e.g., node C 210C) via a data connection (e.g., data connection 273). The receiving/retransmitting node (e.g., node B 210B) encodes on a single twisted wire pair (e.g., data connection 273) the data packets and its local clock (e.g., CLK B).using a 8B10B coding. The second receiving node (e.g., node C 210C) utilizes a phase locked loop (e.g., phase locked loop 252C) (which is coupled to the port that is coupled to the receiving/retransmitting node) to recover the local clock (e.g., CLK B) of the receiving/retransmitting node (e.g., node B 210B). The second receiving node (e.g., node C 210C) utilizes the recovered local clock (e.g., CLK B) to recover the data packets transmitted via a data connection (e.g., data connection 273).
In order to provide a common time reference, a cycle master which is typically the root node 210A synchronizes the cycle counters 230B-230F of the other nodes 210B-210F to the cycle counter 230A of the cycle master (the root node 210A). The root node 210A transmits a cycle start packet every 125 microseconds (or at the start of an isochronous cycle) to the receiving nodes (node B 210B, node D 210D and node E 210E) via data connections 271, 276, and 278. The cycle start packet is transmitted as described above. The cycle start packet includes the value of the cycle counter 230A of the root node 210A. The receiving nodes (node B 210B, node D 210D and node E 210E) copy the value of the cycle counter 230A of the root node 210A to their respective cycle counter 230B, 230D, and 230E. Moreover, the receiving nodes (node B 210B and node E 210E) retransmit the cycle start packet to node C 210C and node F 210F, respectively, so that node C 210C and node F 210F are able to copy the value of the cycle counter 230A of the root node 210A to their respective cycle counter 230C and 230F.
Since the cycle start packet is synchronized to the local clock at each intermediate node prior to retransmission, a propagation time is introduced to the cycle start packet. This propagation time is a source of jitter in the respective cycle counters of the nodes. Moreover, the respective cycle counters 230B-230F(which are incremented by respective local clocks CLK B-CLK F) can lead or lag the cycle counter 230A of the root node 210A prior to receiving the cycle start packet. This translates directly to jitter in the respective cycle counters 230B-230F, causing distortion in any data processing operation that uses the respective cycle counter 230B-230F as a time reference.
FIGS. 3A-3D illustrate the relationship over a period of time between the local clocks of the nodes of the conventional 1394b data bus system of FIG. 2, showing the source of jitter in the respective cycle counter of the nodes. As discussed above, each local clock operates at a nominal frequency of 25 MHz. CLK A is the local clock of the root node 210A, whereas the cycle counter 230A of the root node 210A is incremented by CLK A. As described above, the root node 210A synchronizes the cycle counters 230B-230F of the other nodes 210B-210F to its cycle counter 230A by transmitting a cycle start packet that has the value of the cycle counter 230A of the root node 210A. CLK B is the local clock of node B 210B. CLK C is the local clock of node C 210C.
At t=T1 (FIG. 3A), CLK B leads CLK A by b1 seconds. At t=T2 (FIG. 3B), CLK B lags CLK A by b2 seconds. At t=T3 (FIG. 3C), CLK B lags CLK A by b3 seconds, where as b2 greater than b3. At t=T4 (FIG. 3D), CLK B leads CLK A by b4 seconds, whereas b1 greater than b4.
At t=T1 (FIG. 3A), CLK C lags CLK A by c1 seconds. At t=T2 (FIG. 3B), CLK C leads CLK A by c2 seconds. At t=T3 (FIG. 3C), CLK C leads CLK A by c3 seconds, where as c2 greater than c3. At t=T4 (FIG. 3D), CLK C lags CLK A by c4 seconds, whereas c4 greater than c1.
FIGS. 3A-3D illustrate that the phase of CLK B with respect to CLK A drifts over time. Moreover, FIGS. 3A-3D illustrate that the phase of CLK C with respect to CLK A drifts over time.
These clock phase drifts cause the propagation time of the cycle start packet to fluctuate and cause the cycle counters 230B-230F to drift with respect to the cycle counter 230A of the root node 210A prior to receiving the cycle start packet, resulting in jitter in the cycle counters 230B-230F of nodes 210B-210F; It is difficult to filter out this jitter. Since the cycle counter provides a common timing reference for processing data packets, the jitter distorts and degrades the processing of the data packets. In particular, if the data packets include digital audio data, the jitter distorts and degrades the sound reproduced with the digital audio data.
A method of synchronizing each local clock to a master clock in a data bus system is described. In an embodiment, the data bus system includes a plurality of nodes each having a local clock, whereas the data bus system is compliant with the 1394b specification. In addition, each node includes a local clock generator, one or more ports, and one or more clock recovery circuits each coupled to a respective port. Initially, a clock source for each local clock is the respective local clock generator of each node.
During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. The first identifier is a parent port and the second identifier is a child port. If a node has a first identifier port, the node changes a clock source for its local clock from the local clock generator to a particular clock recovery circuit that is coupled to the first identifier port. The particular clock recovery circuit recovers a transmitted local clock of a transmitting node that is coupled to the first identifier port, whereas the transmitting node has a second identifier port which couples to the first, identifier port. The plurality of nodes includes a root node, whereas the root node does not have a first identifier port and has at least one second identifier port for transmitting its local clock to another node. Hence, the local clock of the root node serves as the master clock for synchronizing the local clocks of the other nodes, reducing jitter in the cycle counters of the nodes when the cycle counters are updated with the value of the cycle counter of the root node.
In another embodiment, the data bus system includes a plurality of nodes each having a local clock, whereas the data bus system is compliant with the 1394b specification. In addition, each node includes one or more ports and a multiple mode clock recovery circuit, whereas the multiple mode clock recovery circuit operates in each of a plurality of modes including a locked mode and an unlocked mode. Initially, a clock source for each local clock is the respective multiple mode clock recovery circuit (of each node) operating in the unlocked mode.
During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. The first identifier is a parent port and the second identifier is a child port. If a node has a first identifier port, the node changes a clock source for its local clock from the multiple mode clock recovery circuit operating in the unlocked mode to the multiple mode clock recovery circuit operating in the locked mode. The multiple mode clock recovery circuit operating in the locked mode recovers a transmitted local clock of a transmitting node that is coupled to the first identifier port, whereas the transmitting node has a second identifier port which couples to the first identifier port. The plurality of nodes includes a root node, whereas the root node does not have a first identifier port and has at least one second identifier port for transmitting its local clock to another node. Hence, the local clock of the root node serves as the master clock for synchronizing the local clocks of the other nodes, reducing jitter in the cycle counters of the nodes when the cycle counters are updated with the value of the cycle counter of the root node.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
In one embodiment, the present invention includes a method of synchronizing a plurality of local clocks in a data bus system having a plurality of nodes, each node having one of the plurality of local clocks, the method comprising the steps of: a) initiating formation of a data bus configuration for the data bus system, wherein each node includes a local clock generator, at least one port, and at least one clock recovery circuit coupled to a respective port, wherein a coupled port represents a port coupled to another port; b) for each node, assigning each coupled port one of a plurality of identifiers based on predetermined criteria the identifiers including a first identifier and a second identifier; and c) for each node which has a first identifier port, changing a clock source for a respective local clock of the node from a respective local clock generator of the node to a particular clock recovery circuit of the node, wherein the particular clock recovery circuit recovers a transmitted local clock of a transmitting node coupled to the first identifier port via a second identifier port.
In another embodiment, the present invention includes a method of synchronizing a plurality of local clocks in a data bus system having a plurality of nodes, each node having one of the plurality of local clocks, the method comprising the steps of: a) initiating formation of a data bus configuration for the data bus system, wherein each node includes at least one port and a multiple mode clock recovery circuit (MMCRC), wherein the MMCRC operates in each of a plurality of modes the modes including a locked mode and an unlocked mode, wherein a coupled port represents a port coupled to another port; b) for each node, assigning each coupled port one of a plurality of identifiers based on predetermined criteria the identifiers including a first identifier and a second identifier; and c) for each node which has a first identifier port, changing a clock source for a respective local clock of the node from the MMCRC operating in the unlocked mode to the MMCRC operating in the locked mode, wherein the MMCRC operating in the locked mode recovers a transmitted local clock of a transmitting node coupled to the first identifier port via a second identifier port.